1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device in which a high speed output operation is required.
2. Description of the Prior Art
A typical example of a semiconductor device is a semiconductor memory device such as a DRAM (Dynamic Random Access Memory). FIG. 18 shows NMOS sense amplifiers 101 and a sense amplifier driving transistor 100 used in a DRAM. When the potential at a common source line 102 of the NMOS sense amplifiers 101 is one half (1/2)Vcc of the supply voltage Vcc, a control signal to drive the NMOS sense amplifiers 101 is supplied to the gate of the sense amplifier driving transistor 100. Then, the sense amplifier driving transistor 100 is turned on to initiate the sense operations of the NMOS sense amplifiers 101.
In such a prior art semiconductor memory device, a peak current flows through the sense amplifier driving transistor 100, as shown in FIG. 19, at the instant of switching on the sense amplifier driving transistor 100, i.e., at the start of the sense operations of the NMOS sense amplifiers 101. When the peak current flows, the potential of the ground to which the sense amplifier driving transistor 100 and other internal circuits are commonly connected rises, thereby causing noises to be generated in such internal circuits.
The sensing sensitivity of a sense amplifier, in general, decreases as the current flowing through the sense amplifier increases, and, therefore, the presence of the peak current also presents the problem of decreasing the sensing sensitivity of the NMOS sense amplifiers 101 at the start of the sense operations. The peak current can be reduced by reducing the size of the sense amplifier driving transistor 100. However, when the size of the sense amplifier driving transistor 100 is reduced, there arises another problem in that the sense operations of the NMOS sense amplifiers 101 take a longer time period to complete.
The above-mentioned problems occur also at the start of an output operation of a semiconductor device in which, as shown in FIG. 20, a line 103 connected to an output of the device is to be pulled down by a pull-down transistor 100.